In the fabrication of semiconductor devices such as field-effect transistors, miniaturization of device geometry has been an important goal not only to provide minimized device size, but also to improve certain device performance characteristics, such as operating speed and frequency response. In the formation of these semiconductor devices, a lithographic process (such as described by William S. DeForest in the book entitled "Photoresist Materials and Processes", McGraw-Hill Book Company, New York, N.Y., 1975) is used to define a pattern having openings of predetermined dimensions, which, in turn, define predetermined regions on the device being formed. Ultraviolet radiation has been used for many years to expose a variety of known photoresist materials. However, this technique is not presently satisfactory for certain high resolution fabrication processes since the ultraviolet radiation itself has limitations with respect to its diffraction and resolution characteristics which are dependent upon the wavelength of the ultraviolet radiation. Thus, in order to overcome these limitations, other resist exposure technologies have been developed which use radiation with wavelengths shorter than those of ultraviolet radiation. One of these new technologies involves the use of a beam of electrons to expose a desired fine pattern in a resist material.
Using one prior art electron beam lithographic process as described, for example by J. P. Ballantyne, in the article entitled "Electron Beam Fabrication of Chromium Master Masks", in the Journal of Vacuum Science Technology, Vol. 12, No. 6, Nov.-Dec., 1975, pp. 1257-1260, a metal film is deposited on the surface of the substrate. The metal film is used to subsequently form a metal pattern on the substrate and further serves to subsequently remove negative charges from the electron beam which strikes the substrate so that the substrate does not accumulate a negative charge which would repel additional electrons aimed at the substrate. Next, a thin film, typically one micrometer or less, of a resist material which is sensitive to electron beams is deposited over the metal film. Then, a beam of electrons is used to expose predetermined areas of the resist, either by transmitting the electrons through a suitable mask structure or by successively positioning the electron beam under the direction of a computer program. Next, the exposed resist is developed with a selected solvent which takes advantage of the enhanced dissolution rate of the molecules of resist that were fragmented by exposure to the electron beam. During the development of the exposed resist, the cross-sectional profile of the opening formed depends on the developer solvent. The more active the developer, the greater the influence of increased development time on the profile of the opening and the larger the opening. The walls of the opening formed in the resist may be vertical (i.e., normal to the surface of the substrate), may slope inward from the substrate surface to the top surface of the resist, or may slope outward from the substrate surface to the top surface of the resist, depending on the developer and the conditions used. The vertical wall profile is the most commonly used geometry in the fabrication of devices of submicrometer dimensions.
After the exposed resist has been developed, there remains a resist mask having a pattern of openings in predetermined regions. Then, the portions of the thin metal film exposed by the patterned openings in the resist mask are removed by chemical etching. Finally, the resist mask is removed from the surface of the metal layer by a selective solvent, to leave behind a patterned metal layer having a predetermined configuration. One major disadvantage of such a process is that control of line width is difficult to achieve. During etching of the exposed resist, etching occurs along the width of the desired line pattern as well as along the depth. This isotopic etching causes the etched lines to become wider than desired. In addition, when the metal layer is etched through the patterned resist, the resist material may be attacked by the etchant, which causes the resist material to be lifted and causes the formation of widened and ragged etched metal lines. Also, during the metal etching process, contamination or damage to the surface of the substrate may occur.
In forming devices of submicrometer dimensions, it is desirable to form the contact area of the gate electrode with the substrate, or the gate length, as small as possible in order to increase the frequency and gain at which the device can operate. On the other hand, it is also desirable to decrease the parasitic resistance of the gate electrode, which can be achieved by increasing the total area of the gate electrode. One approach to this problem has been to form a gate electrode with a large aspect ratio (height-to-width ratio), for example, a height of 1.5 micrometers and a width of 0.5 micrometers, which provides a small gate electrode contact area and a large total gate electrode area. However, such electrodes with a large aspect ratio are difficult to fabricate using a standard lithographic process in which the metal layer must be deposited over a patterned resist layer to a thickness of, for example, 1.5 micrometers and then a standard resist lift-off process must be performed in order to form the desired thick metal gate electrode. One basic difficulty in such a process is that as the metal layer is built up by conventional evaporation techniques to form the thick metal gate electrode, it is also built up on the patterned resist layer and this gradually causes a constriction in the pattern opening formed in the resist layer. When forming devices of small dimensions, this constriction, in turn, causes a reduction in the amount of metal deposited along the length dimension of the gate being formed. As a result, the gate so formed has tapered sides and reduced cross-sectional area, which are undesirable in this instance. In addition, the mechanical stresses imposed on a tall, thin metal electrode formed by such prior art processes, particularly for widths less than 0.5 micrometers, tend to tear the metal electrode away from the surface of the substrate. Furthermore, during the lift-off process, the metal layer must be severed to remove the undesired metal and such a severance is difficult to achieve to produce a smooth, reproducible edge when the metal layer is thick.